Phase locked loop systems, also known as phase locked loops, are used for a wide variety of purposes, such as frequency synthesizers and phase modulators in transceivers for wireless communications devices such as GSM (Global System for Mobile communications), PCS (Personal Communication System), PCN (Personal Communications Network), and DECT (Digital Enhanced Cordless Telecommunications) devices.
In a divide-by-N phase locked loop (“PLL”), a reference signal at a reference frequency is input to a phase/frequency detector along with a feedback signal derived from the output of the PLL. The output of the frequency/phase detector is connected to a charge pump. The filtered output of the charge pump is applied to a voltage controlled oscillator to generate an output signal at the desired frequency. The output signal frequency is divided by a value of N using a counter that functions as a frequency divider, the carryout signal of which forms the feedback signal input to the phase/frequency detector.
In a divide-by-N PLL, the output frequency cannot be varied in steps any smaller than the reference frequency. This limitation has led to the development of fractional-N phase locked loops. In a fractional-N phase locked loop, the value of N is changed over time so that changes in frequency in steps less than the reference frequency can be realized.
In this fractional-N type of PLL, it is desirable to synchronize the transmission to the counter of the new value of N with the completion of the previous count. However, it is also necessary to synchronize the generation of the new values of N with the reference frequency. Unfortunately, these two events are asynchronous. This leads to dithering between the completion of the previous count and the generation of the new value of N. This dithering may result in new values of N not being loaded into the counter and/or the same values of N being loaded into the counter twice. Either event can cause frequency and/or phase errors in the output of the voltage controlled oscillator.
What is needed is a technique to prevent errors in dithering. Additionally, when such a PLL is used as a digital phase modulator, it is necessary for the phase data to be synchronized to the reference frequency. If phase data is supplied to the PLL asynchronously, a technique for synchronizing the phase data to the reference frequency is also needed. Moreover, it would be helpful to have general techniques for modifying electromagnetic waves in phase locked loop devices as well as other similar devices to meet needs in the art.